SRAM memories in complicated micro controller products have to be tested frequently in safety applications during the application in order to detect, to correct and to register resulting new hard errors and soft errors in the memory. This is executed in short regular time slices and takes a substantial amount of time of the actual application. The shorter the time required for regularly testing the memory, the more time and performance is available for the actual application.
In conventional systems, SRAM modules are tested by first of all functionally switching off modules whose SRAM was to be tested and then making the memory accessible via the bus and then transferring (copying) the actual application content into a different memory which is still empty and then testing the memory to be tested using a predefined algorithm/physical occupation. After the test, the actual content is copied back again.
Shifting the original user data via a bus is very time-consuming. Likewise, the test frequently executed by the CPU is often not really able to simulate critical conditions during active operation as the CPU accesses the memory via a slow bus with waiting cycles during the test while the module which uses the memory possibly accesses each cycle one after the other.